A principal objective of damascene circuit interconnect manufacture is to create metal isolated by and embedded in a dielectric media. Modern copper electroplating for damascene processes proceeds by a “bottom up” fill mechanism that preferentially fills high aspect ratio features such as deep trenches and vias on a wafer surface. The preferential filling of recessed requires careful control of process conditions. Mayer et al., U.S. Pat. No. 6,946,065 entitled “Process for Electroplating Metal into Microscopic Recess Features”, incorporated herein its entirety for all purposes, describe some of the issues one must consider in performing filling operations. For the most part, prior processes do not preferentially fill and planarize low aspect ratio features and therefore they require significant excess metal deposition (“overburden”). Overburden is the additional copper deposited on the substrate to ensure that all low aspect ratio features are completely filled (essentially in an isotropic fashion) to the plane of the wafer isolating dielectric surface (the “field”). Since the preferential “bottom-up fill” does not occur in low aspect ratio features, the surface of the overburden typically follows the contours of these underlying wafer surface recesses over these features. In most cases, the overburden on field regions is slightly thicker than the thickness of the damascene layer, typically on the order of 1.2 or more times the depth of the deepest feature. For example, a damascene structure that has 0.5 micrometers deep features will typically require an overburden of at least approximately 0.7 to 0.8 micrometers.
The fact that the filling of low aspect ratio features is largely isotropic leads to very little, if any, reduction in the overall topography of the surface. The step change in the low aspect ratio features is essentially identical to the initial patterned recess depth in the dielectric media. When combined with overplating or momentum plating associated with high aspect ratio feature, the net topography variation using current technology generally increases during the plating operation, and is approximately equal to the sum of the step height of the dielectric film thickness and the highest overplated high aspect ratio feature. A goal of the manufacturing steps is to eventually isolate the individual lines within the recesses of the device dielectric layer. However if metal was subsequently isotropically removed, then these low aspect ratio features would lose all the metal below the plane of the dielectric before the high aspect ratio lines and field area metal was removed. A planarization or polishing technology that removes metal more rapidly from raised regions than recessed region is therefore used so that, at the end of the metal removal steps metal remains in these low aspect ratio features. Chemical mechanical polishing is one technology that is used to accomplish this end. But to use these polishing planarizing technologies, “overburden” is required. An desirable alternative would be to employ a process where the metal in recessed features is deposited more rapidly than other areas.
Overburden is undesirable for a number of reasons. It requires deposition of excess copper that is essentially wasted. It requires an extra step of removing the overburden material. Thus, overburden represents additional materials costs (excess copper deposited and removed) as well as decreased throughput/productivity. Overburden is typically removed by a planarization technique such as chemical mechanical polishing (CMP), electrochemical chemical polishing (eCMP) or other electropolishing techniques suited to planarize low aspect ratio features. The CMP and eCMP processes are particularly expensive process and implement generally corrosive chemical and slurry formulations on large pads to polish the surface of the integrated circuit. Polishing can be difficult to control and the polishing end-point can be difficult to detect. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP and eCMP. Also, with the introduction of porous low-k dielectrics in semiconductor devices, modification of traditional CMP and even eCMP processes will be required, as current methods can lead to cracking and/or delamination of low-k materials which are fragile and typically have a very low compression strength.
Measures must be taken to avoid metal “dishing”, dielectric/line “erosion”, and underlying topography during CMP. See, for example, “Establishing the discipline of physics-based CMP modeling, S. R. Runnels, and T. Lauren, Solid State Technology, March, 2002. Dishing occurs on the interconnect metal primarily over larger features and contact pad region during the later stages of copper CMP. Because electroplating creates variations in thickness over the dielectric, and because underlying topography is transferred to higher levels through the dielectric from lower levels, within-die variations in the amount of metal thickness over the dielectric continue to always exist and persist up to the point of the first clearing of interconnect metal over the damascene structure (barrier exposure). Because neither the metal deposition (e.g., electroplating) nor metal removal (e.g., CMP) processes are perfectly uniform across the wafer surface, global non-uniformities also exist. Dishing of a feature generally occurs when the metal has cleared locally around the periphery of the feature but the polishing process must be is continued over that feature to complete the process elsewhere. This “overpolishing” is needed, for example, because other areas of the surface have not reached the clearing endpoint. The pad tends to terminate and is “held up” at the feature periphery by the barrier film (supported by the underlying dielectric). The barrier material is largely unaffected (i.e., removed at a much slower rate) as the CMP of copper on the surface continues. The problem arises that the interconnect metal (e.g., copper) in the feature is slowly removed, preferentially within the feature, hence it becomes “dished”. It is believed desirable to ensure that all the interconnect metal (copper) above the barrier/dielectric level is removed from the top of the barrier/dielectric at this point in the process before proceeding with removing the typically conductive barrier film, so significant “overpolishing” is often needed and significant dishing can occur. After interconnect (copper) removal above the field is complete, the barrier layer is exposed. If properly performed, the barrier is largely unaffected by this process. During the subsequent barrier/dielectric step of the CMP process, one needs to avoid excessive erosion. Erosion arises from locally varying polishing property of different area of the surface. This is believed due to the different CMP rates and mechanical “strength” of the substrate at different point on the circuit. Varying feature density and the different mechanical properties of the metal and dielectric are the leading causes of polishing erosion. In the barrier/dielectric removal/polish CMP steps erosion can be viewed as primarily a mechanically driven process. Most topography has been removed at this stage. After the barrier has been removed and the dielectric is exposed, a goal of polishing is to eliminate dishing in the early copper CMP step without causing erosion of high-density area of lines. To eliminate the dishing, some amount of dielectric is removed but this reduces the thickness of the copper interconnects and increases the electrical resistance. The overall changes in the planarity caused by dishing, erosion, and underlying topography can also lead to difficulties in obtaining good focus across the die during subsequent lithographic steps. Also important, topography introduced by these effects is replicated at the next metal level, creating “underlying topography”. These areas are particularly troublesome for CMP technology because of the competing requirements of having planarization and compliance. Clearing metal by CMP from recessed areas of “underlying topography is difficult, often leaving “puddles” of metal. To remove these “puddles,” the CMP process is generally continued for a longer period of time than otherwise desirable because it can create excessive dishing.
While not intending to be held to any specific theoretical explanation, this background helps to explain the interrelationship between the types of planarization phenomena often encountered (dishing, erosion, puddles) and illustrates the problems of the current art. These issues make CMP progressively more difficult with advancing technology requiring additional numbers of metal layers to be added to the structure.
Alternatives to CMP include electrolytic etching techniques such as electropolishing or electroless etching. Compared to CMP, these are relatively low cost techniques. They also provide much higher processing rates. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution, the reverse of electroplating.
Although many previous approaches address the need for simpler and improved electroplanarization in semiconductor device fabrication, they generally address alternative planarization techniques performed after deposition of an undesirably thick overburden with substantial variations topography. Yet electroplating processes that deposit copper with reduced overburden, reduce and/or control the variation of topography, or improve planarity, are highly desirable.
J. Osterwald and J. Schulz-Harder (“New Theoretical Ideas about the Action of Bath additives”, Galvanotechnik, 66, 360, [1975] and “Leveling and Roughening by Inhibitors and Catalysts”, Oberflache-Surface, 17, 89, [1976]) proposed a smoothing and filling mechanism and action of a strongly surface-attached accelerating molecule that enables preferential growth. Others demonstrated the usefulness of this concept in interpreting, modeling and controlling preferential filling of small damascene features. See, for example, J. Reid and S. Mayer, in Advance Metalization Conference Proceedings, 1999, pg 53; A. C. West, S. Mayer, and J. Reid, Electrochem. Solid-State Lett., 4, C50, [2001]; T. P. Moffat, D. Wheeler, W. H. Huber, and D. Josell, Electrochem Solid State Lett, 4, C26, [2001]; and T. P. Moffat, D. Wheeler, and D. Josell, Electrochemical Society Interface, pg 46, Winter 2004.
Another class of methods useful in overburden reduction and planarization is referred to as “brush plating” or “planar plating”. These methods generally employ a brush that acts on the surface to achieve smoother deposits during the plating process. So-called bottom-up fill (also referred to as “superfilling”) methods are now commonly used to fill high aspect ratio (i.e., deeper than wide) recess features, though a geometric acceleration concentration mechanism similar to that proposed by Ostwald et. al. and later made practical. However, the physical and geometrical limitations of these processes, mean that they are not capable of filling low aspect ratio features Since both high and low aspect ratio features can exist on every damascene integrated circuit interconnect level, there is interest in any potentially low cost “planar plating” method. Various planar plating methods that attempt to modify the otherwise conformal plating behavior over recessed low aspect ratio region by modifying the plating method (bath additives, transport properties, field effects, etc.) have been reported.
Schwartz (U.S. Pat. Nos. 3,183,176, 3,313,715 and 3,939,134) describes a method and apparatus for brush planar electroplating for preparing smooth electrodeposits, diminishing surface roughness and preferentially filling recessed small crevices. Macula et al. (U.S. Pat. No. 3,751,343) also describe a brush plating apparatus and process where electrolyte is held in and simultaneously moves through a rubbing surface element with electrolytic plating with an orbital rubbing like motion. Eisner (U.S. Pat. Nos. 3,619,383 and 3,749,652) describes an apparatus and method of brush plating which uses simultaneous abrasion of the surface to reduce roughness and accumulation of unwanted metal deposition.
The following documents are incorporated herein by reference in their entireties and for all purposes: Controlini and Mayer (U.S. Pat. No. 5,486,234); Controlini and Mayer (U.S. Pat. No. 6,315,883); Controlini et al. (U.S. Pat. No. 6,709,565); Koos et al., U.S. patent application Ser. No. 10/690,084, entitled “Method for Fabrication of Semiconductor Interconnect Structures with Reduce Capacitance, Leakage Current and Improved Breakdown Voltage, filed Oct. 20, 2003; U.S. Pat. No. 6,176,992; Reid (U.S. Pat. No. 6,024,857); Bulent et al. (U.S. Pat. No. 6,534,116); U.S. patent application Ser. No. 11/739,822; Reid (U.S. Pat. No. 6,653,226); and International Patent Application No. WO 2005/042810 entitled “Membrane Mediated Electropolishing” in the names of Mazur et al.